Solution

Given:

Four stage pipeline is used

Delay of stages = 150, 120, 160 and 140 ns

Delay due to each register = 5 ns

1000 data items or instructions are processed

Cycle Time:

Cycle Time =  Maximum delay due to any stage + Delay due to its register

⇒  Max { 150, 120, 160, 140 } + 5 ns

⇒  160 ns + 5 ns

⇒  165 ns

Process:

Pipeline time to process 1000 data items

⇒ Time taken for 1st data item + Time taken for remaining 999 data items

⇒  1 x 4 clock cycles + 999 x 1 clock cycle

⇒  4 x cycle time + 999 x cycle time

⇒  4 x 165 ns + 999 x 165 ns

⇒  660 ns + 164835 ns

⇒  165495 ns

⇒  165.5 μs

The Correct Answer is 165.5 μs